Major 

VLSI Design
 
 
 Research Interests

Design Verification

Logic Synthesis & Testing

ASIC Design

  
 
 Education 

Ph.D., University of Massachusetts, U.S.A., 1990
 
 
 Selected Publications 
  1. Park, S., Yang, S., and Cho, S., "New Optimal State Assignment Technique for Partial Scan Designs," IEE Electronics Letters, Vol. 36, No. 18, pp. 1527-1529, 2000.

2. Lee, D., and Yang, S., "Intelligent Timing Optimization in Hierarchical Designs," Journal of KIPS, Vol. 6, No. 6, pp. 1635-1645, 1999.

3. Yang, S., "FatBaby : Multi-functional Rapid Prototyper for IP-Based System Designs," Proceedings of International Workshop on Advanced LSI`s and Devices, pp. 44-49, 1999.

4. Kim, H., Bae, Y., Park, I., and Yang, S., "FSM State Assignment Using Genetic Algorithm," Journal of KISS, Vol. 24, No. 9, pp. 837-845, 1997.

5. Yang, S., "Logic Transformation for Concurrent Partial-Scan-Testability/Timing-Optimization," Proceedings of Conference on SIG CAD and VLSI, pp. 31-36, 1997.
  
 
 Professional Experiences 

Associate Professor, School of Electrical and Computer Engineering, Pusan National University (1991-Present)

Senior Researcher, MCNC, U.S.A. (1990-1991)

  
 
 Professional Societies & Activities 

Member, IEEE, IEEK, KISS
  
 
 Honors and Awards 

  
 
 International Joint Research & Activities